This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-269223 filed on Sep. 5, 2000, the entire contents of which are incorporated herein by reference.
This invention relates to a semiconductor memory device and, more particularly, to a nonvolatile ferroelectric memory device.
Semiconductor memory is currently used in all electric products including main memory devices of large-scale computers, personal computers, household electric appliances, cellular phones and others.
Various kinds of semiconductor memory such as volatile DRAM (dynamic RAM), SRAM (static RAM), nonvolatile MROM (mask ROM), flash EEPROM (electrically erasable programmable memory), and so on, are commercially available. Among those, DRAM is volatile but currently occupies almost all of the market because of its advantages in the sense of its cell area being xc2xc as compared with SRAM and its speediness equivalent to flash EEPROM.
On the other hand, since electrically erasable programmable flash EEPROM is nonvolatile, it permits cut of power. However, it involves such drawbacks that, for example, the rewritable frequency (W/E frequency) is in the order of only 106, and therefore it takes the order of micro seconds for writing and a high voltage (12V through 22V) is required for writing, its market is not yet so wide as that of DRAM.
In contrast, nonvolatile memory using a ferroelectric capacitor (ferroelectric memory) has been under development by various manufacturers since it was proposed in 1980 because it has advantages, namely, nonvolatility, rewritable frequency as high as 1012, read and write time equivalent to that of DRAM, operability under 3V through 5V, and so on, and it might possibly replace the entire memory market.
FIG. 18 shows a conventional ferroelectric memory cell MC1 having one-transistor and one-capacitor, its cell array, sense amplifier and dummy cell circuit. FIG. 19 is a timing chart showing their behaviors.
As apparent from FIG. 18, each memory cell of the conventional ferroelectric memory is made up of a transistor and a capacitor connected in series. A cell array is a matrix arrangement of such memory cells, and includes bit lines/BL, BL for reading data, word lines WL0, WL1 for selecting a memory cell transistor, and plate lines PL0, PL1 each for driving one end of a ferroelectric capacitor. The sense amplifier is connected to the bit lines, and the dummy cell circuit is disposed symmetrically to the memory cell.
Behaviors of the ferroelectric memory are explained with reference to FIG. 19.
In an active mode where the memory cell MC1, for example, has been selected, the word line WL0 connected to MC1 is HIGH and the plate line PL0 is HIGH. As a result, memory cell data is read out to one of a pair of bit lines pre-charged to VSS. In case of this example, cell data is read out to the bit line /BL (/BLSA), and the potential of the bit line rises. If the memory cell data is xe2x80x9c1xe2x80x9d, then polarization of the ferroelectric capacitor is reversed, and the bit line is raised to a high potential. If the memory cell data is xe2x80x9c0xe2x80x9d, then polarization reversal does not occur, but potential of the bit line rises as much as the paraelectric component of the ferroelectric capacitor and the capacitance ratio of the bit line capacitance.
In this manner, although the bit line potential rises from Vss for both data xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d, there is a difference between the potentials. Therefore, if the reference bit line BL (BLSA) can be adjusted to an intermediate potential between those potentials, it is possible to determine whether the cell data is xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d by amplifying the difference between the bit line and the reference bit line with the sense amplifier.
Conventionally, potential of the reference bit line was generated using a dummy cell circuit as shown in FIG. 18. In a standby mode, the transistors Q1 and Q2, in which dummy word lines SWL0, DWL1 are connected to gates, are turned OFF, and one end N1 of the paraelectric capacitor C1 is pre-charged to the source potential of Q3, i.e. Vss, by turning the transistor Q3 ON. In an active mode, a transistor of a dummy word line connected to the reference bit line, which is the transistor Q1 in this example, is turned ON to connect BL and N1, and then the potential of the dummy plate line, which is the other end of C1, is raised from Vss to VDC potential. Through these operations, potential Vref of reference BL can be raised from Vss to the intermediate potential between those corresponding to xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d data by coupling of the paraelectric capacitor C1.
However, the dummy cell circuit system of FIG. 18, reviewed above, involved the following problems. For example, in the 0.5 xcexcm rule class, the bit line capacitance CB is about 1000 fF. In case a memory cell capacitor having the area of 3 xcexcm2 is used, if the potential at the HIGH side of the bit line amplitude is 3V (=Vaa), then the read-out potential to the bit line of xe2x80x9c1xe2x80x9d data is about 1.2 V in average of all cells whereas the read-out potential to the bit line of xe2x80x9c0xe2x80x9d data is about 0.4 V in average of all cells. Therefore, 0.8 V is required as the reference bit line potential, and taking account of fluctuation of ferroelectric capacitors, a reference potential to the level of 1.5 V (=xc2xd Vaa) including estimation for distribution is required.
In order to generate the reference bit line potential of xc2xd Vaa by using the conventional dummy cell circuit shown in FIG. 18, a very large paraelectric capacitor is required. Its reason will be explained below.
FIG. 20 shows value of reference bit line potential Vref under the condition in which the capacitance of the paraelectric capacitor C1 of the dummy cell circuit is CD, bit line capacitance is CB, and source potential for the dummy cell is VDC ((0 less than VDCxe2x89xa6Vaa): here let the maximum value be Vaa). The reference bit line potential is a value obtained by dividing VDCxc3x97CD, which is the charge of the surplus for raising the paraelectric capacitor CD from Vss to VDC, by the total capacitance (CB+CD). Therefore, to obtain xc2xd Vaa potential, a large paraelectric capacitor capacitance CD (=1000 fF) equal to the bit line capacitance CB is required. Then, if MOS capacitors of 8 nm are used, a dummy cell capacitor as large as 225 xcexcm2 is required, and the chip size will increase significantly. More specifically, to generate Vref of 1 V, capacitance as large as CD=xc2xdCB is required, and to generate of Vref of xc2xd Vaa or more, CB less than CD. Thus, CD itself becomes a load capacitance, and there is a large difficulty.
These problems were conventionally avoided by using two other methods.
On of these methods uses a ferroelectric capacitor used in a memory cell to make up such a dummy capacitor without using a paraelectric capacitor such as MOS capacitor having a small dielectric constant. With this method, since the ferroelectric material has a very large dielectric constant, a small dummy cell circuit can be realized.
This method, however, involves the following drawbacks, among others,
1) capacitance value of the ferroelectric capacitor itself largely fluctuates;
2) the ferroelectric capacitor changes in value due to fatigue if it is subjected to polarization reversal;
3) capacitance value of the ferroelectric material decreases when polarization takes place; and
4) characteristic of the ferroelectric capacitor changes due to generation of imprint. So, it is preferable that the paraelectric capacitor is usable.
The second of those methods raises the plate potential in the read-out mode to bring about polarization reversal of the memory cell and read out a signal, and uses the bit line potential after being lowered to Vss as the read-out potential.
In this case, since the plate line potential returns to the original value beforehand, there is the effect that no paraelectric component of the memory cell capacitor is recognized. Therefore, both the xe2x80x9c1xe2x80x9d data potential and xe2x80x9c0xe2x80x9d data potential become low potentials, and a dummy cell even of a small paraelectric capacitor can generate a sufficient reference bit line potential.
This method, however, involved the following drawbacks.
1) since sense-amplifying operation takes place after the plate line is raised and lowered, random access time becomes very long, and
2) since it needs operations of again raising and lowering the plate line upon re-writing data, it results in raising and lowering the plate line twice, and cycle time becomes very long.
The Inventor has already proposed, in U. S. Pat. No. 5,903,492, as nonvolatile ferroelectric memory, a new type of ferroelectric memory simultaneously satisfying three requirements, namely,
(1) memory cell of a small size,
(2) planar transistor easy to manufacture, and
(3) versatile random access function.
FIG. 21 shows configuration of that earlier ferroelectric memory, and FIG. 22 shows an example of its operations. Since that earlier invention also uses the same read-out principle as the conventional ferroelectric memory, it similarly uses the dummy cell circuit shown in FIG. 21, which is similar to FIG. 18, for generating the reference bit line potential.
In its standby mode, the transistors Q1, Q2 of the dummy word lines are turned OFF and the transistor Q3 is held ON, one end N1 of the paraelectric capacitor C1 is pre-charged to the source potential of Q3, i.e. vss potential.
In an active mode, a transistor of a dummy word line connected to the reference bit line, which is the transistor Q1 in this example, is turned ON to connect BL and N1, and then the potential of the dummy plate line, which is the other end of C1, is raised from Vss to VDC potential. Through these operations, potential Vref of reference BL can be raised from Vss to the intermediate potential between those corresponding to xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d data by coupling of the paraelectric capacitor C1.
Therefore, also in the earlier application, problems shown in FIGS. 19 and 20 occur. As compared with the conventional ferroelectric memory, the bit line capacitance in the earlier application is about xc2xc per cell, and the number of cells for each sense amplifier (bit line) can be increased to 4 times. In this case, the number of dummy cell circuits themselves can be reduced to xc2xc, and influences of the area of the dummy cells are not so large as the conventional ferroelectric memory. Nevertheless, it still occupies several % of the chip area, and reduction of the dummy cell area is desirable. For example, in case the number of cells per bit line is xc2xd and a reduced amount of CB is used for enhancing signals, CB is about 500 fF in the 0.5 xcexcm rule class, and in case a memory cell capacitor with the are of 3 xcexcm2 is used and the HIGH side potential of the bit line amplitude is 3V (=Vaa), the read-out potential to the bit line of xe2x80x9c1xe2x80x9d data is about 1.5 V in average of all cells and the read-out potential to the bit line of xe2x80x9c0xe2x80x9d data is about 0.5 V in average of all cells. Therefore, 1 V is required as the reference bit line potential, and taking account of fluctuation of ferroelectric capacitors, a reference potential to the level of 1.5 V (=xc2xd Vaa) is required. In order to generate the reference bit line potential of xc2xd Vaa by using the conventional dummy cell circuit as shown in FIG. 21, a very large paraelectric capacitor as shown in FIG. 20 is required similarly to the conventional ferroelectric memory. To obtain xc2xd Vaa potential, a large paraelectric capacitor capacitance CD (=500 fF) of the same value as the bit line capacitance CB has to be used . Then, if MOS capacitors of 8 nm are used, a dummy cell capacitor as large as 112 xcexcm2 is required, and the chip size will increase significantly. Also for generating Vref of 1 V, capacitance as large as CD=xc2xdCB is required, and for generating of Vref of xc2xd Vaa or more, CB less than CD. Thus, CD itself becomes a load capacitance, and there is a large difficulty.
As reviewed above, the conventional ferroelectric memory and the ferroelectric memory of the earlier application involved the problem of an increase of the chip size because of the need for a large capacitor area when using a paraelectric capacitor to generate a high reference bit line potential. The method of generating the reference bit line potential by using a ferroelectric capacitor to remove that problem involved problems of variance, deterioration, decrease and fluctuations, and involved the problems of undesirable change in reference bit line potential and a decrease of the signal read-out margin. Additionally, although there is a method for avoiding the problems by raising and lowering the plate line twice and thereby lowering the reference bit line potential, the method had the problem of a slow operation.
According to an embodiment of the invention, there is provided a semiconductor memory device comprising:
a plurality of memory cell blocks each including a serial connection of at least a plurality of memory cells each including a cell transistor and a ferroelectric capacitor connected in parallel between source and drain terminals of said cell transistor;
a plurality of word lines connected to said cell transistors;
a plurality of bit line pairs connected to said memory cell blocks;
a plurality of amplifier circuits connected to said bit line pairs to amplify a signal difference between bit lines in each of said bit line pair; and
a dummy cell circuit to generate a potential for one of said bit line pair, which is a reference bit line to which data is not read out from said memory cells, said dummy cell circuit including at least one paraelectric capacitor;
wherein in a standby mode, a first terminal of said paraelectric capacitor is pre-charged to first potential higher than ground potential, and a second terminal of said paraelectric capacitor is pre-charged to ground potential; and
in an active mode, said first terminal is connected to said reference bit line, and said second terminal is raised from ground potential to a second potential higher than ground potential.
According to another embodiment of the present invention, there is provided A semiconductor memory device comprising:
a plurality of memory cell blocks each including a serial connection of at least a plurality of memory cells each including a cell transistor and a ferroelectric capacitor connected in parallel between source and drain terminals of said cell transistor;
a plurality of word lines connected to said cell transistors;
a plurality of bit line pairs connected to said memory cell blocks;
a plurality of amplifier circuits connected to said bit line pairs to amplify a signal difference between bit lines in each of said bit line pair; and
a dummy cell circuit including a first dummy cell portion having a first paraelectric capacitor to generate a first potential of a first bit line of said bit line pair and a second dummy cell portion having a second paraelectric capacitor to generate a second potential of a second bit line of said bit line pair,
wherein a first terminal of the first paraelectric capacitor is connected to the first bit line via a first transistor and to a first dummy cell power supply potential via a second transistor, and a second terminal of the first paraelectric capacitor is connected to a first dummy plate line, and a first terminal of the second paraelectric capacitor is connected to the second bit line via a third transistor and to a second dummy cell power supply potential via a fourth transistor, and a second terminal of the second paraelectric capacitor is connected to a second dummy plate line.
According to further embodiment of the present invention, there is provided a semiconductor memory device comprising:
a plurality of memory cells made up of a serial connection of cell transistors and ferroelectric capacitors;
a plurality of word lines connected to said cell transistors;
a plurality of bit line pairs connected to said memory cells;
a plurality of amplifier circuits connected to said bit line pairs to amplify a signal difference between bit lines in each said bit line pair; and
a dummy cell circuit for generating a potential in one of bit lines in each said bit line pair, which is a reference bit line to which data is not read out from memory cells, said dummy cell circuit having at least one paraelectric capacitor;
wherein in a standby mode, a first terminal of said paraelectric capacitor being pre-charged to a first potential higher than ground potential, and a second terminal of said paraelectric capacitor being pre-charged to ground potential; and
in an active mode, said first terminal being connected to said reference bit line, and said second terminal being raised from ground potential to a second potential higher than ground potential.
According to still further embodiment of the present invention, there is provided a semiconductor memory device comprising:
a plurality of memory cells each including a serial connection of a cell transistor and a ferroelectric capacitor;
a plurality of word lines connected to said cell transistors;
a plurality of bit line pairs connected to said cell transistors;
a plurality of amplifier circuits connected to said bit line pairs to amplify a signal difference between bit lines in each of said bit line pair; and
a dummy cell circuit to generate a potential for one of said bit line pair, which is a reference bit line to which data is not read out from said memory cells, said dummy cell circuit including at least one paraelectric capacitor;
wherein in a standby mode, a first terminal of said paraelectric capacitor is pre-charged to first potential higher than ground potential, and a second terminal of said paraelectric capacitor is pre-charged to ground potential; and
in an active mode, said first terminal is connected to said reference bit line, and said second terminal is raised from ground potential to a second potential higher than ground potential.
According to yet further embodiment of the present invention, there is provided a semiconductor memory device comprising:
a plurality of memory cells each including a serial connection of a cell transistor and a ferroelectric capacitor;
a plurality of word lines connected to said cell transistors;
a plurality of bit line pairs connected to said memory cell blocks;
a plurality of amplifier circuits connected to said bit line pairs to amplify a signal difference between bit lines in each of said bit line pair; and
a dummy cell circuit including a first dummy cell portion having a first paraelectric capacitor to generate a first potential of a first bit line of said bit line pair and a second dummy cell portion having a second paraelectric capacitor to generate a second potential of a second bit line of said bit line pair,
wherein a first terminal of the first paraelectric capacitor is connected to the first bit line via a first transistor and to a first dummy cell power supply potential via a second transistor, and a second terminal of the first paraelectric capacitor is connected to a first dummy plate line, and
a first terminal of the second paraelectric capacitor is connected to the second bit line via a third transistor and to a second dummy cell power supply potential via a fourth transistor, and a second terminal of the second paraelectric capacitor is connected to a second dummy plate line.